With the development of the display technology, higher requirements are now imposed on the resolution of display products and thus higher requirements are imposed on the fabrication process of array substrates.
FIG. 1 schematically illustrates a plan view of a structure of a prior art array substrate. As shown in FIG. 1, a portion of each gate region G corresponding to a respective pixel unit N extends to the pixel region and has a large area, which is almost the area of the whole gate region G. Hence, the portion of the gate region G that extends to the pixel region has a large edge length. In the fabricate process of such an array substrate, as a cleaning solution flows to clean an active layer which has been formed, much of the metal from the active layer tends to remain at the edges of the gate region that extend to the pixel region. Since the active layer residual contains N+ conductive metal, a short circuit will be readily caused by the residual conductive metal between a pixel electrode and a data line in a region indicated with the dotted line box in FIG. 1 after fabrication of a source and a gate on the array substrate. Therefore, upon a subsequent monochromic image lighting test, an electrical current will flow from the pixel electrode to the adjacent data line due to the residual active layer metal, leading to a reduction of a voltage on the pixel electrode and hence its capability of driving liquid crystal to deflect. This results in dark points in the displayed image, which affect the quality of the displayed image.
Therefore, how to reduce the residual of active layer metal along the edges of the gate region in the array substrate fabrication process is a technical problem to be solved by those skilled in the art.